Smarter Utility

 

TMCNet: Xelerated Releases Software Development Kit 5.0

[October 08, 2009]

Xelerated Releases Software Development Kit 5.0

Oct 05, 2009 (Close-Up Media via COMTEX) -- Xelerated, a provider of Carrier Ethernet and Unified Fiber Access ASSP-based chipsets, announced it has launched the latest release of its Software Development Kit (SDK), the SDK 5.0.

Designed to support Xelerated's HX Carrier Ethernet network processors (NPUs) and AX Programmable Ethernet Switches, SDK 5.0 enables vendors to optimize network design for Carrier Ethernet platforms and devices.

Xelerated said its SDK 5.0 supports all device types of the two families - allowing system vendors to seamlessly develop and customize data plane software for their unified fiber access and next generation Metro Ethernet platforms. The SDK 5.0 instruction set and programming model are compatible with previous NPU generations, thus easing reuse of existing applications and migration of code for existing X11 customers that are looking to optimize their data planes with the capabilities of new generation Carrier Ethernet devices.


"At Xelerated, we want our customers to have the right tools available to make the most out of the new Carrier Ethernet devices," said Fredrik Orava, VP of software at Xelerated. "With the SDK 5.0, vendors can jumpstart their design processes for the new generation of unified fiber access and Metro Ethernet products that service providers are demanding. We look forward to seeing how these projects unfold and how platforms are being developed for the next level of packet processing capabilities, intelligent aggregation and integration." As with previous generation NPUs by Xelerated, the HX and AX Carrier Ethernet families of devices leverage dataflow architecture, with a deterministic pipeline of processor cores that allows for data plane programming models. For example, a processor's code can be written with a single instruction set using a straightforward sequential programming model. An attribute of the dataflow architecture is that once the code is compiled, wirespeed performance is guaranteed for all packet sizes and services, the company noted in a release.

((Comments on this story may be sent to newsdesk@closeupmedia.com))

[ Back To Homepage ]